| Convolutional coding is a type of channel coding. It is widely used in communication systems, such as satellite communication and wireless communication. Viterbi algorithm is a maximum likelihood decoding algorithm for convolutional codes and it has been considered as the best decoding algorithm for its advantages of good decoding performance, high speed and simple decoder structure. With the development of programming logic technology, the implementation of the Viterbi decoder based on FPGA becomes a mainstream design method. As different convolutional codes used in the different communication systems, a re-configurable Viterbi decoder is more useful to meet the system requirements.A High-Speed Viterbi decoder has been implemented based on FPGA in this paper. The implementation algorithm of the Viterbi decoder key modules are expatiated after thorough study of Viterbi algorithm. In the design, the branch metric module only calculates possible metrics each time, saving the resource. The add-compare-select module designed with full parallel structure to achieve higher speed. The survivor path management module implemented based on 3-pointer even algorithm whose pipeline structure accelerates the decoding. A Viterbi decoder for (2,1,7) convolutional code is designed with VHDL in Xilinx ISE 8.2i as a prototype. The Viterbi decoder can be used for the (2,1,7), (3,1,7), (2,1,9) and (3,1,9) convolutional codes by modifying relative parameters. Some other parameters, such as decoding length, can also be modified.In order to get the soft information which is used for simulation and testing, a communication system is designed based on Simulink. Functional and timing simulations processed in ModelSim SE6.0. Timing report shows the highest clock frequency of the Viterbi decoder is up to 200MHz. Further testing processed on the hardware platform built up with FPGA and DSP. The BER performance of the Viterbi decoder is nearly equal to the Viterbi decoder module in Simulink by simulating. |
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