Cmos Ic Esd Protection

This thesis includes physical analysis for the turn-on mechanisms of several ESD protection devices during ESD stress and the applications of submicron/ deep-submicron CMOS integrated circuit ESD protection design , so that CMOS IC is protected from being damaged.With CMOS ICs process development, the device feature size has been shrunk to deep-submicron for the improvement of IC performance and operation speed, and this also reduces the cost of IC fabrication. But, because of the reduction of the device feature size, the Junction Breakdown voltage of semiconductor device has approached the Gate-oxide breakdown voltage, the design of IC's ESD protection becomes more and more difficult. Through the research of the thesis, it is very important to understand and grasp the ESD protection circuit design concepts and strategy for the selection of the best ESD protection solution.First, manufacturers and users of Ics have derived the ESD test methods from the basic ESD stress models: the Human Body Model(HBM) and the Charged Device Model(CDM). The ESD test for the same I/O pin maybe find the different results because they select different test methods. ESD test standards specify how an IC has to be stressed in an ESD test system. They specify the chip ESD robustness is determinded by the lowest voltage of all I/O pins of the chip rather than the highest voltage of all I/O pins of the chip. Moreover, the failure model and failure meschanisms of electrostatic damage provide the foundation to understand the problem of the ESD damage.Second, to understand the turn-on mechanisms of ESD protection device during ESD stress, the turn-on characteristics of those devices must be analyzed. According the ESD protection circuit design concepts and strategy, ESD protection circuit can be designed to effectively protect IC from being damaged. To enhance CMOS integrated circuit ESD protection capability, the thesis includes the improvement of the process , the improvement of the device and the improvement of the circuit. ESD protection device in the thesis includes diode, bipolar, NMOS(PMOS) and SCR(silicon-controlled rectifier), among them SCR is the best ESD protection device.Finally, Full ESD protection design has became an important issue for integrated circuits in advanced deep-submicron CMOS process. ESD protection is not only the issue of the I/O pin ESD protection design, but also the issue of the whole chip ESD protection design. When ESD damages are found in the I/O pin, the problem is easy to be solved. However, ESD damages are found taking place in the internal circuit, even in the mixed-mode IC interface, it is very exhausting and difficult work to exactly locate the place where ESD damage take place. Therefore, the ESD protection design must be considered at the integrated circuit research stage, in advance which keep away all kinds of ESD damages that the integrated circuit maybe meet.