Research And FPGA Implementation Of A Dual-Mode Digital Down Converter In DVB-T Terminal

With the development of digital television technology, the tendency for broadcasting television to move from analog to digtal becomes irresistable. Being the minutest, most matured and widly used standard among all existing terrestrial broadcasting standards in world, DVB-T (Digital Video Broadcasting-Terrestrial) can give us referential experience in developing our own terrestrial standard.Being an important component of DVB-T receiver, digital down converter shifts digital IF signal to baseband so as to decrease the data rate. After being processed, the decreased signal can meet the demand of baseband processor so that the following modules can achieve realtime processing. In this paper, after completing the DVB-T transmit-receive system simulation, we designed and implemented a Dual-mode Digital Down Converter which can be used in DVB-T receiver. Two modes share the Numerical Control Oscillator. The choice of using which Decimation Filter depends on the inputs: If the bandwidth of input signal is 6MHz, the decimation factor is 4. If the bandwidth of input signal is 8MHz, the decimation factor is 3. In the whole designed system, the main modules are completed by using CORDIC Arithmetic, cascaded Half-Band-Fileter and Nyquiest Filter. The final simulation shows the results can meet the design requests: BER<1×10^-3, MER>21dB. Different from other traditional DDC, the architecture we desgined here can meet the needs of later DDC ASIC implementation.The main features and contributions of this paper are as follows:1. Designed a Dual-mode DDC according to DVB-T (6MHz/8MHz) terminal's request. Lower down the area and power by special designed parameters and architectures.2. Realized NCO by using CORDIC algorithm, a high speed multiplier which should work under 192/7MHz is saved.3. Optimize the architecture of filter circuit by using CSD encode theory and multipath structure.Now this Dual-mode DDC has been implemented and verified in Xinlix VirtexII serial FPGA. Finally it is proved that FPGA implementation can meet design request.