Design Of An 8-bit SCM Based On RISC Architecture

In this thesis, an integrated digital circuit IP core of 8-bit Singlechip Microcomputer (SCM) based on RISC architecture is designed by Top-Down IC design method. Harvard bus that instruction bus and data bus are seperate is adopted as bus scheme. Two level pipe-line structure is introduced. Clock resource is distributed reasonable. Taking instruction and performing are executed simultaneously. Furthermore, the SCM is based on reduced instruction set computer (RISC) architecture that is easy to learn and use, and there are only 35 instructions. As a result, the hardware resources are shared as many as possible, the circuit architecture is optimized, and most of the instructions can be executed in one machine cycle. The performance goal is fulfilled. Power consumption is reduced and system speed is increased.The system specification, compartmentalization and design of sub modules, logic synthesis, functional simulation, etc. are described in details in this thesis. The reduce principle is abided in the design course. The optimization of architecture and area makes the number of components to be reduced as few as possible. The research of Addrx Mux, Controller and ALU are emphasized, especially the improvement of ALU. As a result, the bottle-neck of performance advance is broken. The comparator control circuit widens the application area of this SCM.I am responsible for the system specification, compartmentalization and design of sub modules, logic synthesis and functional simulation. This SCM is completely compatible with PIC16C622 of Microchip incorporation so that the software can be replant directly. Design tools are mainly the Cadence and Synopsys incorporations'. The achievement of this project would greatly promote the development of the system on chip (SOC).