System Level Simulation Modeling Of All-Digital FM IBOC DAB And Front-End ASIC Design Of Models

Digital audio broadcast system (DAB) is the third wireless radio system, it have more excellent advantages than traditional AM. Because of pursuing good quality of sound and digital operations, all digital FM IBOC DAB has become an interesting topic recent years.First, based on discussion the key technology of IBOC DAB system, a software platform which simulates a in-band on-channel baseband transmission for the all digital FM radio system is done. After comparing and analyzing kinds of channel corrected, modulation and channel estimation, and utilizing correlation of bit error ratio and subjective audio quality and considering the realization complexity and computation, Rapid assessment of system capacity could be performed, synchronization and accelerate the simulation is also discussed. The simulation results show that the scheme with time interleaving depth of 332ms for Serial Concatenated Convolutional Code (SCCC),16QAM modulation and 1/32 guard interval duration could get better capacity.Then, This paper presents a low power and high-speed 24×24-b multiplier with modified booth encoder. For low power design, it uses the operator isolation and clock gating glitch free. This multiplier has been verified in FPGA and implemented in chartered 0.35 micron CMOS standard cell technology, with its frequency being 50MHz and its area 14329.74 gates, power 24.69 mw. This architecture is compared with some other architectures using the same technology, and the result shows that it is effective and efficient. Furthermore, a design of low power scalable pipelined booth multiplier with modified booth encoder for ASIC is designed, and RTL codes coverage analysis is completed.The multiplier detects the input operands for their dynamic range and accordingly implements a 4x4 bit unsigned, 8×8 bit and 16×16 bit signed fixed point, 32×32 bit floating point multiplication operation. The multiplication mode is determined by the dynamic range detection unit, which generates and dispatches the control signals for the latched-based pipeline stages. It has been implemented in chartered 0.35 micron CMOS standard cell technology. With its frequency being 80MHz, the proposed scalablepipelined booth multiplier proves to be globally 34.8% more power efficient than a non-scalable pipelined booth multiplier, and it has fast speed due to 5 stage pipeline.Finally, the scrambler,RS(204,188) encoder, time interleaver, punctured convolutional encoder, frequency interleaver and 16 QAM mapping circuit is designed , they are also integrated as a single module. Functional verifications indicate correction. Then, integrated module verification is done based on Matlab verification plantform using the 256x256 Lena as testcase. it is showed that the receiver bit error ratio is 8.524×10^-5 which is lower than 10^-4 .in the urban fast channel model, adding gauss white noise for 18 db, the PSNR of Reconstructions of Lena image is 35.32.it is proved integrated module has better performance.