A High-Speed Low-Power Modulo 2(n)+1 Multiplier Design Using Carbon-Nanotube Technology

Modulo 2n+1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this thesis, a new circuit implementation of a high-speed low-power modulo 2n+1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the final adder stage. The major technical contribition to the arts of the thesis is that the partial product reduction stage introduces a new MUX-based compressor to reduce power and increase speed. Secondly, in the final adder stage, the sparse-tree based inverted end-around-carry adder reduces the number of critical path circuit blocks. Finally, a proposed adder is implemented using both 32nm CNTFET (Carbon-Nanotube FET) and bulk CMOS technology for comparison. The CNTFET-based design dramatically decreases the PDP (Power Delay Product) of the circuit. The simulation results demonstrate that the MUX-based compressor reduces the PDP of the partial product reduction stage by 4.24 times compare to the traditional full adder based design. The sparse-architecture solves the wire interconnection problem while slightly reduces the PDP of the final adder stage compare to the Kogge-Stone design. The power consumption of CNTFET-based multiplier is on average of 5.72 times less than its conventional bulk CMOS counterpart, while the PDP of CNTFET is 94 times less than the CMOS one. The proposed multilier circuit and its implementation demonstrates the viability of the ultra-low-power and high performance feature of the promising CNTFET technology.