| Fast Fourier Transform is a necessary precondition of digital spectral analysis as the basic computing between the time domain and frequency domain. The traditional FFT uses software or DSP to realize, which is difficult to meet real-time in high speed processing. Application specific integrated circuit (ASIC) and programmable logic device (represented by field programmable gate array, FPGA) arises at the historic moment. ASIC has the advantage in the speed, but the chip area will expand rapidly with the processing points increasing, which means the improvement of costs. While FPGA contains hardware multipliers, massive memory cells and programmable I/O, so it is very suitable for implementation of FFT processor. Therefore, FPGA is low-cost, easy to debug and can be repeatedly programmed. It has more market competitiveness.In this paper, the design and implementation methods of the 1024-point FFT processor in FPGA is proposed.(1)This method uses Radix-4 DIT algorithms and 5-stage pipeline structures, and improves the design of butterfly processor and pipeline structure. It can save around 75% of hardware area and also greatly enhance the computing speed, so as to achieve the requirements of high-speed and real-time system.(2)It designs built-dual-port RAM to store data, for it is easy-control, and fast.It also uses ROM to store twiddle factors, and gets numbers through lookup table to save time.(3)To avoid data overflow, block floating-point structure is used, which is a good compromise between fixed-point and floating-point. It also saves device resources.(4)Finally, the authentication for the FFT algorithm for hardware implementation through the Matlab simulation results proves that the method proposed by this paper is correct. The experimental results show that the method of computing not only ensures the accuracy and implementation complexity, but also improves the clock frequency of the data processor and processing speed. It achieves the desired goal. |
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