The Research And Improvement Of FPGA Low-Power Placement & Routing Algorithm

With FPGAs' development, placement and routing takes more than 60% of all resources. At the same time, cellular devices make higher requirement to the system's area and power consumption. It will improve FPGAs' performance by make better architecture and placement and route algorithm.In this paper, we mainly research two aspects, FPGAs' routing track distributions in heterogeneous FPGA architecture with embedded hard macro and placement algorithm modification. Four architectures, whose routing channel width distribution functions are uniform, Gaussian, pulse and delta, are investigated. The source code was updated to make VPR suitable for FPGA with hard macro architecture, and then a set of MCNC benchmark circuits were used to test four architectures' area-efficient. The experiment result, whose objective is average wire length, shows that, compared with others, uniform routing track distribution architecture has the most outstanding performance.In improving placer algorithm, we implemented Ant Colony Optimization (ACO) algorithm, whose performance is quite good in solving TSP problem, in FPGA placement. Simulated Annealing algorithm is widely used in FPGA placer nowadays, but its searching process is totally random. It only uses an objective function to decide whether the CLB selection is acceptable or not, and has no impact on choosing CLB process, which makes the searching time-wasting. ACO mimics natural ants' behavioral, using pheromone for exchanging information between ants. It enhances the pheromone on the trail, which can shorten the whole system's cost, by an objective function. More and more trails that can improve system's performance involved in the best solution with time going, and finally find a good solution in a reasonable time. The result shows that the system's performance using ACO, without optimizing its parameters carefully, has almost as better as the one using SA.