Research And ASIC Implementation Of ARM Core Based On0.18μm Standard CMOS Process

As the embedded system apples and develops in consumer electronics andmany other fields, miniaturization,low power consumption andcan-be-customized become a trend of independent research and developmentof the processor core.The ARM core, as a business core, is known for its popularity andreliability.It has been the market leader for many years. Therefore, howto design a core with similiar function to the business core, compatiblewith their development environment, and of which the details can becustomized and tailored kernel became the contents of this paper.This thesis is composed of five elaborations.First, ARM core’s architecture. Describe the architecture, instructionset, data cache and instruction of cache ARM core.Second, to descrip the specific functions of ARMv4core by Verilog.Third, to upload the binary document into test platform and emulate thecore by Modelsim software.Fourth, to configure the FPGA resources, to generate a ROM and RAM, towrite programs into FPGA and to achieve board-level verification.Fifth, to backend design by ASIC and the technology of0.18μm standardCMOS.This author designs a core which can use ARM RISC based on three-levelpipeline. The core has already been analyzed in principle and instruction,then we got the RTL description. The author use both FPGA and ASIC technology.Finally, We got the layout. This core is available in function and technique.