Optimization And Analysis Of FPGA Placement And Routing Algorithm

Placement and Routing are important parts in Field Programmable Gate Array(FPGA) supporting software, which establish the mapping relation between the logiccircuit and specific FPGA chips. In supporting software, the quality of Placement andRouting algorithm is closely related to the efficiency of the whole software, thecorrectness of the final chip function and the performance of the chip.In this thesis, the FPGA structure is introduced first. Then, the XML language isemployed to descript the FPGA structure semiformally and model the FPGA chiparchitecture. The method can separate the placement tool from specific FPGA chip. Atthe same time, Aiming at the low efficiency of the classical simulated annealingalgorithm used in placement of VPR, this thesis develops two placement algorithmsbased on parallel simulated annealing algorithm with considering the advantage ofparallelization in dealing with large scale problems. After a detailed analysis of twoalgorithms, their influences on the final placement results are presented. In the end, westudy and analyze parameters of the placement algorithm and give some modifiedopinions, which improve the flexibility of the placement algorithm, and makes itpossible to be adjusted according to the chip in the specific application.