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The Research Of Pixel-level ADC For CMOS Image Sensor

Posted on:2007-09-11Degree:MasterType:Thesis
Country:ChinaCandidate:Y J WangFull Text:PDF
GTID:2178360212480066Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The improvement of Integration provides the opportunity to implement the digital camera. By redistributing the processing down to the pixel level, the image sensor can achieve new imaging capabilities, higher image quality, and more significant reduction in system cost and power. In this paper, we focus on the pixel-level Analog-to-Digital Conversion (ADC) for image sensor. It is the main work of"A Million-Pixel-level CMOS Image Sensor with Wide Dynamic Range in Deep Submicron Process", a project of National Natural Science foundation of China. The works I have done are as follows:(1) Designed a simple multichannel bit-serial (MCBS) ADC. Traditional bit-parallel ADC techniques require an m-bit latch at each pixel to implement m-bit conversion, which waste layout area. The MCBS ADC is implemented using a 1-bit comparator/latch pair per four neighboring pixels, and a ramp generator/controller shared by all pixels.(2) The ADC works at Nyquist rate. It uses successive comparisons to output one bit at a time simultaneously from all pixels. The comparator/latch pair operates at very slow speeds and can be implemented with simple robust circuits.(3) Low-light performance is improved to the level of analog CMOS sensors by using direct integration instead of continuous sampling. Lag is eliminated by resetting the photodetectors after A/D conversion is performed.(4) Designed a comparator with cascode output which operates in subthreshold to maximize gain and minimize power consumption.(5) Designed a ramp generator which implements higher precision with simple structure. The ADC with it can readily implement variable step-size quantization. The ADC has been designed in chrt 0.35um 2P4M, n-well standard CMOSprocess. For 8-bit resolution, the ADC conversion time is about 2.08ms, and the sample rate is about 3.84kS/s. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It achieves 121.48 um2 pixel size at 25.36% fill factor. With a 3.3V power supply, every 2×2 pixel block dissipates less than 1uW.
Keywords/Search Tags:CMOS Image Sensor, pixel-level ADC, MCBS, Comparator, Subthreshold region, Ramp generator
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