Research On CMOS Image Sensors With High Dynamic Range Pixel And High Speed Low Power ADC

CMOS image sensors are very widely used nowadays because of their low cost and high integration.In recent years,the CMOS image sensor technology has made a great progress in terms of performance and cost.Nowadays,not only used in low end consumer and suvillence applications,you can also easily find CMOS sensors in many high-end applications such as scientific,industrial,space,etc.All these applications are used to be dominated by Charge Coupled Device imagers in early times.Over the past 20 years,CMOS image sensors has earned a huge market success which in the end forces the the large institutes and companies to invest more in its research.High speed,high dynamic range(DR),low noise,low dark current,and global shutter are some key features that requested in these high-end applications.Dynamic range defines ratio of the largest and smallest signal that image sensor can detect.Human eyes are able to detect more than 160 d B of DR,while most of the image sensors can only detect around 70 d B.Request for DR extending of a CMOS image sensor is ever growing.Various methods to enhance the DR of a CMOS imager have been presented in recent years.In system level,many camera makers first capture multiple images with different exposure time,and then combine them into one to extend the DR,this method is very simple and straightforward.Most image sensors can support this because change of exposure time is an intrinsic property.Problem with this method is the image may show ghosting effect if the scene contains moving objects.In some literatures,logarithmic response CMOS pixel is used,the DR can be increased to more than 120 d B,at the expense of higher dark noise and fixed pattern noise(FPN)compared with normal CMOS imagers because of no CDS.It is also possible to achieve high DR by transferring the photodiode charges to two floating diffusion with different capacitance,and then combining the image signals from the two floating nodes.Adding one transistor and one capacitor based on the 4-T pixel can realize the dynamic change of pixel conversion factor during readout.However,the fill factor is reduced as these extra transistor and capacitor require more area and routing placed inside the pixel.In this thesis,dual gain pixel without additional capacitor is proposed and verified with test chip and a well-designed CMOS image sensor.With 6.5um pixel size,87-d B of intrascene DR is achieved,the pixel without ?lens gives a fill factor of 64.8%.The characterization result matches quite well with our expectation.Nowadays almost all CMOS image sensors contain Analog to Digital Convertor(ADC)on chip.This simplifies the design of camera board and also lowers the total cost.Column level ADC architecture is normally used these days in CMOS image sensors.It gives a compromise on speed,power consumption and complexity compared with chip level and pixel level ADCs.There are a variety of column-parallel ADC architectures such as ramp ADC,successive approximation,and cyclic ADC,etc.Among all of these architectures,ramp ADC is the most widely used because of its simplicity and easy usage.While with so many columns of counting blocks and high-speed counting clocks,sometimes counting induced power consumption and substrate noise can be a problem especially when low noise and low dark current are required.In this thesis,we propose a dual clock counting algorithm for Ramp ADC.Comparing to the conventional ADC architecture,the proposed method can significantly reduce the power consumption by reducing the number of counts with two clocks at different frequencies.During the AD conversion,low speed clocks are used for counting most of the time,while high speed clock is used for counting only for a short period.Theoritically for a 12-bit ADC,the power consumption can be reduced to 1/32 compared with previous one clock counting.The implementation of this method makes it possible to use such ADC structure in a large resolution sensor with relatively small digital power consumption.A 4M image sensor was designed and fabricated to verify the functionality and effectness of power saving with the proposed dual clock counting.Results are also presented in this thesis.The main problem for Ramp ADC is the conversion speed when increasing the ADC bit depth.The easiest way to solve this is to boost the counting clock frequency.But the clock quality can give problems especially when the counting clock goes up to more than several GHz.Also the power consumption increases linearly with the clock frequency which will degrade the dark current performance.Recently several methods to lower the conversion time without increasing clock frequency have been published.In some literature,phase-shifted clocks or codes are used for counting.Complicated data processing is needed in order to cover the clock phase alignment and variations between different columns.Compared with single edge slope ADC used in CMOS image sensors,double edge counting can half the conversion time without increase the counting clock frequency.In this thesis,we propose a power and area improved double edge concept.It can be implemented together with double clock counting architecture we proposed and verified also in this thesis,which is very suitable for low power and small pixel pitch column ADCs of CMOS image sensors.A fabricated 25 M CMOS image sensor is used to verify this ADC.Only 3?s is needed for the 12-bit conversion with 960 MHz maximum counting clock frequency.Functionality of the sensor is verified and characterization results are presented.