| Effective Digital Image Processing (DIP) algorithms require robust computational resources, which can be costly in terms of speed and power consumption for any embedded image sensor application. A remedy for this is a focal plane implementation. In this design, the image filtering occurs within the hardware of the image sensor at real time before being sent to an interfacing CPU. This thesis presents a monolithic implementation of a programmable multipass image processing hardware, capable of spatial and temporal image filtering at the focal plane in IBM 0.18 microm CMOS technology. It has with an additional feature that enables multiple filtering. The novel architecture has a unique pixel write-back that gives it the ability to perform repeated processing in the analog domain, thus making it ideal for low power, low cost image sensor applications that require the image to be filtered more than once. To further enhance the performance of the image processing hardware, each pixel has its own ADC. The fabricated CMOS camera-on-chip consists of 128 by 64 arrays of pixels with a fill factor of 27%. The prototype design can achieve 900MOPS/mW, which could be improved. |
