Design And Simulation Of Memory BIST Based On March C+ Algorithm

With the development of information technology, designs become more complex, and embedded memory has been taking more and more area in SoC (system-on-a-chip). Because of the high density of the embedded memory, it is much easier to result in faults on the chip and therefore to degrade yield. Now, chip testing issue has become a bottleneck restricting the scale of the integrate circuit. The traditional Auto Test Equipments (ATE) can not meet the test demand of very large scale integrate circuit, so, BIST (Build-In Self-Test) method has been used in the memory test.In this paper, the main fault models of memory are analysed and the comparison between the main methods of embedded memory test are made. It is probed that MBIST (Memory Build-In Self-Test) is an effective method of memory test. On the basis of researching on relevant MBIST theories, we particularly analyse the March algorithm, then we elicit that March C algorithm is an effective method which can detect many memory faults.The top-down method is used in the MBIST design, and the VHDL hardware description language is used to program the entire system. The implementation of MBIST circuit design is based on Finite State Machine (FSM) and an improved March C algorithm——March C + algorithm is employed, the design is simulated by simulation tool——ModelSim SE 6.2b, then the whole design is verified to be correct.This design optimizes conventional circuit structure of MBIST. Test vector generator, address generator and read or write controller are integrated in a BIST controller module, So that the structure of the system is more reasonable and the difficulty of design is degraded. At the same time the design avoids difficulty of debugging about excessive communications signals between different modules, and economizes the area of chip. Under the condition that the system clock frequency is 5MHz and simulated time accuracy is 1ns, the total time is 2.1701ms to accomplish the whole MBIST, so achieves the purpose that the test time is short. It is universal about intellectual property (IP) of the design, when we design other memory test system, we only need amend the bit of I/O (input/output) interface in the IP. Then it can be used in other memory test system, so the IP has well portability.