RAM BIST Design Based On SoC Chip

Today,the on-chip system on chip(SoC)has developed rapidly.With the increase in the level of integration,the circuit design has become more complex.The feasibility of chip testing and test power consumption have also begun to attract attention..The improvement of the quality of chip testing,the reduction of testing costs,and the shortening of test time have become the focus of people's attention during the chip testing process.The traditional chip test method mainly relies on the manual writing of test vectors,and the test efficiency is low.Moreover,due to the limited level of the test machine and the limited testing resources,the large-scale production of the complexity of modern chips has not been applied.In order to avoid the failure of the SoC chip in the production process,Design For Testability(DFT)has become an essential step.There are many methods for testability design.For the test of memory in SoC chips,the most widely used method is built-in self test(BIST).The beginning of this article mainly introduces the development status and basic principles of chip testing.Then introduced a variety of testability design methods,through comparison,analysis of the advantages and disadvantages of various methods.Next,the failure of common memory is introduced.The characteristics of the three IPs of the SoC chip that need to be tested simultaneously determine the use of the BIST design method.Because the BIST test circuit structure has the characteristics of test generation and test response running in the circuit,it can generate test excitations and analyze test responses without external support,so that the test effect is better.By focusing on the March algorithm in the memory test,the March C+algorithm for proper memory testing is found.Today,this algorithm is relatively perfect in the development of chip testing,and it can detect common faults in the chip memory.On this basis,the project uses the Perl language to call the script to generate the March C+ algorithm,and designs the BIST-related hardware circuit.The BIST design is simulated using the built simulation platform VCS and Verdi tools,and the simulation is performed on the BIST design.That is to simulate the RAM fault in theBIST design.Simulation results show that the test method proposed in this paper can effectively achieve the test results.This method can be extended to test other chips and has strong applicability.The BIST structure based on the March C+ algorithm is the main research direction of future chip memory testing.It has the advantages of faster operation speed,smaller area,reusability and higher fault coverage,and has a good development prospect.The innovation of this research is on the one hand to solve the insufficiency of the traditional test of SoC chip,using the built-in self-test in the testable design,and selecting the March C+ algorithm to make the chip test fault coverage higher.On the other hand,using the Perl language script to invoke the MbistArchitect tool to automatically generate the March C+ algorithm,the algorithm generation time only takes about 3.5s,which is a few minutes or even longer than the traditional generation test algorithm,shortens the generation time of the algorithm and avoids the gradual The tedious process of writing code is more convenient and convenient for debugging.