Electrical failure modes in CMOS logic integrated circuits

This dissertation presents the results of my work in the analysis and testing of defects that can cause elusive failures, failures that cause errors during system operation but are difficult to demonstrate during testing. The difficulty in detecting and diagnosing elusive failures stems from the lack of understanding of the underlying mechanisms and operating conditions that cause these failures.;The goal of the work presented is to identify and study the failure mechanisms and failure modes that can cause elusive failures in CMOS static fully complementary logic integrated circuits, and to propose techniques for their detection. The work is focused on resistive shorts and hot carrier induced degradation, both of which occur frequently in CMOS IC's. Concrete experimental evidence is related to the concept of resistive shorts and new models for gate oxide shorts in p-channel transistors are proposed. Through the use of more realistic models and through simulation work, we identified resistive shorts and hot carrier induced degradation as possible sources of elusive failure. In the presence of these defects or damage, CMOS logic circuit operation is found to be dependent not only on the extent of the defects or damage, but also on the operating conditions such as power supply voltage and operating temperature. It is also shown that resistive shorts can cause pattern dependent faults that can escape tests generated using normal test generation schemes.;Based on the voltage dependence property, a technique called very-low-voltage testing is proposed for the detection of weak CMOS logic integrated circuits that contain resistive shorts or hot carrier induced degradation. It is shown that certain lower-than-normal operating voltages can force malfunction in weak CMOS logic IC's due to these defects or damage while retaining correct function in truly good IC's. This technique is simple, flexible, inexpensive and non-intrusive. It can be applied in preventing, detecting and diagnosing elusive failures in CMOS logic circuits both in production and in the field.;Finally, some experimental results on test structures and commercial chips are presented to validate the assumptions and simulation results presented in this dissertation.