Image Process System Of FED Based On FPGA

Field emission display (FED) is a promising novel flat panel display which has the advantages both of the high brightness of Cathode Ray Tube and the portability of Liquid Crystal Display.This design mainly researches on video signal of FED driving system for improving image based on FPGA technologies and digital image processing. Firstly, analyzed the present problems of FED display quality such as luminance non-uniformity, grayscale loss and high power consumption on FED driving system. Secondly, proposed new methods and thinking from circuit aspect for improving display quality of FED according to the matured digital image processing and FPGA technologies. And such methods have been applied to the low work function printable 25 inch color VGA FED.Lastly,analyzed and evaluated the image quality of FED processed.In this paper, the digital image real-time processing system was a very important part of FED driving circuit system. ALTERA FPGA chip was used to complete operation on reading and writing and timing control of FED image data. The image process algorithms mainly used gray-level transformation in the theory of image enhancement, and the algorithm realized luminance non-uniformity control, gray-level non-linear correction and automatic power control for FED.The circuit design was thus simplified and the stability of the circuit enhanced due to combination of FPGA technologies and digital image processing.APC decreased the request toward FED and enhanced the reliability of FED. Meanwhile, the system had great expansibility, so it could be improved and expanded by changing the program according to the future request for FED image quality.At present, 25 inch color FED sample has been fabricated with the capacity for image processing in our lab.It can display color video and obtains its brightness about 400cd/m2, contrast ratio 1000:1, 256 circuit gray scales.