Design Of Image Process And Display System Using FPGA

With the improvement of real-time image display performance requirements,realtime image processing is moving in the direction of high resolution,high frame rate,high definition,high dynamic range,and high integration.In this way,the requirements for real-time display algorithms are also getting higher and higher.At the same time,the use of software to process images on computers has obvious deficiencies in processing rate and input/output delays.Programmable logic gate arrays(FPGAs)rely on them.The features of fast running speed and portability are very suitable for digital image processing.Therefore,using FPGA to implement real-time digital image processing is becoming one of the research hotspots.Aiming at the problem of the loss of detail in the display of high dynamic range infrared images,this paper presents a dynamic range compression and detail enhancement display algorithm based on wavelet decomposition.First,the image denoised by bilateral filters is decomposed into a base image containing subject information and a detail image containing high frequency information using wavelet transform.Then,using a logarithmic mapping algorithm to perform dynamic range compression on the base image,in order to be able to display a pixel-focused scene,an adaptive contrast adjustment algorithm is used to stretch the compressed image.For the detail image,compression is performed according to the energy ratio before and after the base image is compressed to achieve detail enhancement and noise suppression.Finally,the base image and the detail image are inverse wavelet transformed with weights.Through experimental analysis of infrared data of different scenes,the results show that the image processed by this algorithm has high contrast,rich details and wide adaptation scenes.In order to meet the real-time requirements of infrared image display,this article makes full use of the various resources provided by FPGA,using the ideas of modular design,pipeline,lookup table and cache and other technologies to implement the infrared image display algorithm in FPGA.For the exponential operation,a double look-up table method is used.Based on the division operation,a divider based on the relationship between the dividend and the number of digits is designed.For the logarithmic calculation,a segmentation mapping method is used,thereby improving the speed of image processing and reducing the image processing speed.FPGA resource consumption and system power consumption.The system meets the predetermined requirements in terms of processing speed and processing effect.