Research And Design Of The Clock System On Chip

With the increase of chip complexity ? the requirement for clock system becomes stricter than ever. In the design of VLSI, the clock system design becomes an important topic in today's research. The clock system is usually made up of clock distribution network and phase lock loop (PLL). This paper completed the design of the clock system of the X microprocessor according to its requirement.The paper researched the advanced theories and the design examples of clock distribution network , then designed the clock distribution network according to the requirement of the X microprocessor. In the design, we not only used some advanced theories but also improved them. This paper presented complete technique about the architecture of clock distribution network. And the paper designed a power on circuit for clock system, which enhanced the chip's reliability. In order to reduce the power consumption, we used gated-clock technique. The paper also designed several key circuit modules in the clock distribution network, such as frequency protection circuit, halve frequency circuit, frequency detection circuit etc, all of those circuits' structure is compact and their performance is high.In order to improve the performance of clock system, the paper studied the design of the PLL and improved on a CPPLL, by adding fast locking circuit to shorten locked time of the CPPLL and by improving on an equal swing circuit of VCO to reduce the jitter of the CPPLL. The paper also summed up the theory of the loop filter and gave the whole design process. Then the paper studied the layout technique of PLL, and presented a design method for complete symmetrical structure of VCO's layout. We taped out the CPPLL in 0.18 micron process, the test result of the sample indicates that the performance of the CPPLL is met the design requirements.