TSV Coupling Model And Noise Analysis In 3D IC

Three-dimensional Integrated Circuit(3D IC) using through silicon via(TSV) as vertical interconnects is an inevitable trend of the integrated circuit development, which reduces the length of interconnect, improves the integration density and supports for heterogeneous integration. With the development of TSV technology, Designs of 3D IC based on TSV start to appear. And the current designs of 3D IC generally have a large area of TSVs, while TSVs are designed to multiple channels for redundant structure and the pitches between TSVs can reach tens of micron. However, due to the large parasitic capacitance of TSV which can be tens or thousands of femtofarad, highdensity TSVs as transmission interconnect of high frequency signal would generate coupling noise, which seriously affects the quality of signals and hinders the development of high-density 3D IC. To solve this problem, we start from TSV coupling model to analysis coupling noise. Summarize laws of coupling noise and methods of suppressing coupling noise, which can be used for the formation of EDA tools. The main work is as follows:1. By using TCAD simulation tools, the interconnect model of TSV and the model of silicon substrate are established respectively and form the TSV coupling model with the two. Extract the parasitic parameters of TSV and make an analysis on the laws of model parameters. Moreover optimizations are made on the analytical formulas of parasitic capacitance of TSV and silicon substrate. According to analysis results of the simulation model, the parasitic capacitance of TSV is closely linked to the temperature of environment. For this, an optimization work is done for the analytical formula of TSV parasitic capacitance, which considers the effects of temperature. The new analytical formula of parasitic capacitance is more accuracy and more simple. Based on the basis of multi-conduction transmission line, make an optimization on the model of silicon substrate. Analysis the parasitic parameter of silicon substrate in different situations, and turn the complex parasitic network to a simplified one when studying coupling noise. The improved TSV coupling model is more accurate and simple, which can be embedded in EDA flow and lay a foundation for the follow-up work of coupling noise.2. Based on the TSV coupling model, an analysis of coupling noise of TSV is made by Hspice simulation and some methods for inhibiting coupling noise are put forward. The analysis on coupling noise is discussed in time domain and frequency domain respectively. And summarize the rules of coupling noise when changing the size and position of TSVs. From these rules, we can find ways to suppress the coupling noise, such as inserting buffer units, adding isolation unites, optimizing the size of TSV and so on. By using the given ways respectively, the effects of inhibiting coupling noise are analyzed. Considering the factors of the position, number, driver ability of buffer unit, summarize the influence of those on coupling noise of TSV. And considering the location of isolation units of power and ground, study the influence on nearby TSV. By studying coupling noise of TSV, we have a better understand of the mechanism and the harm of coupling noise. Give methods for inhibiting coupling noise and make a guidance for reliability design of 3D IC.3. Based on the former study, a method is formed to analyze coupling noise of a large-scale of TSVs. Each of the key steps is explained which are GDS analysis, TSV parasitic net establishment, coupling noise analysis and optimizing project. And optimizations are made in typical layout of TSV to make out the minimum safe distance using different methods to reduce the coupling noise of TSV within a tolerable range. Compare the area using different methods to suppressing coupling noise, and analyze which is the proper way to suppress coupling noise at different conditions. By establishing the process to analyze coupling noise of TSV, supports are made for design works of EDA tools of 3D IC. By studying the distribution of TSVs which inhibit coupling noise, guidance is provided on design of TSV distribution of 3D IC.