| With the development of the integrated circuit and the improvement of IP(Intellectual Property)integration technology,the functions of the chips are becoming more and more powerful,and the module structure can be very complicated.The loss caused by the failure of tape-out is increasingly difficult to bear.All these put forward new requirements for the verification of the chip.At the current stage,common ideas of verification mainly include direct verification,randomization verification,formal verification,and FPGA(Field Programmable Gate Array)verification.After comparing the advantages and disadvantages of each verification idea comprehensively,we found that the randomization verification has distinct advantages.In the industry,UVM(Universal Verification Methodology)verification method,which supports the randomization verification better,is widely used,representing the direction and the trend of the verification field.APB(Advanced Peripheral Bus)protocol and UART(Universal Asynchronous Receiver Transmitter)protocol,as common low-speed bus protocols,have the advantages of low power consumption and simple interconnection signals.In this article,DUT(Design Under Test)is a certain APB-UART module designed by our laboratory.This module is critical in the SoC(System on Chip)structure,which works as an essential bridge for communication between the processor and peripheral devices.In the past,the verifition engineers often used FPGA verification or direct verification to test such modules,which consumed many resources but could not fully and efficiently verified the DUT.Therefore,it is of great significance to build a verification platform for this module based on UVM.We built a UVM verification platform for this APB-UART module and completed the verification by verifying various test scenarios.The main work done in this article is as follows:(1)We analyzed this APB-UART module,including protocol specifications,module architecture,the definition of ports,and the information of registers.Then,we formulate a corresponding verification plan.(2)We in-depth researched the UVM and built a verification platform for this module.That platform contains the following part:(a)multiple agent components,which are responsible for driving and monitoring the data of APB port,UART port,and modem port;(b)multiple scoreboard components,which are used for data comparison and inspection;(c)register model with warning mechanism;(d)verification top,verification environment,and other necessary structures.(3)We developed multiple test cases to realize the automatic generation of random stimuli for covering the function points.In the later stage of verification,we changed the constraint conditions and reached the 100% coverage,indicating that the verification platform is designed reasonably and implemented successfully. |
