Development Of The High Speed Analog Signal Acquisition Card

High-speed data acquisition and high capacity real-time memory is important and necessary for acquisition and assessment of radar echo signal. There is rarely acquisition systems that can have two functions at the same time. This high-speed data acquisition card designed is based on PCI bus and have high capacity memory interface. It combines high-speed date acquisition and high capacity real-time memory.The card designed in the dissertation applies analog channel switchover technology and difference clock match technology to implement intersection sampling The analog channel switchover technology branches off one channel signal and matches amplitude and phase. Then when the card collects signals two channel analog AD signal can match together. The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.This dissertation combines hardware descriptive language, production line transfer technology, ping-pang memory technology and FPGA wiring optimization technology to implement data branch and treating. The data treating and control circuit with soft kernel technology. By FPGA optimization technology the card can be more integration and portability.Using oscillograph principle the dissertation designs a set of digital memory oscillograph system implementing pre trigger, center trigger and after post trigger.The dissertation implements acquisition data high speed transfer with PCI bus DMA technology and designs four group high speed streaming disk interface to expand high speed and high capacity memory and implement mass storage.The dissertation uses uniform model building language UML to set up the superior computer drive program model. The dissertation combines the model and program language C++ to implement the practical acquisition card drive program.