The Research Of Preceding Stage Circuit In CMOS Image Sensor

This paper is mainly about a part of research work on a paramount project to tackle in Tianjin Science & Technology Committee"High Performance High Dynamic CMOS Image Sensor Design". It focuses on the research of preceding stage circuit, which is defined as the circuit to pretreat the image signal before analog-to-digital conversion included signal readout circuit, amplifier, noise reduction circuit etc. The preceding stage circuit not only affects the dynamic range of image sensor, but also influences the spread the system functions.The article mainly discusses the circuit design of the modules in preceding stage circuit included the readout circuit in pixel cell, column readout circuit and powerful programmable gain amplifier (PGA). First, it introduces the basic structure and theory about the readout circuit in active pixel cell, and design the circuit to expand the dynamic range and fill factor (photo-sensitivity), and analyse the chip test result. Secondly, the column readout circuit structure, which used double sampling technique to eliminate the fixed pattern noise (FPN) from pixel cell, is improved by offset compensation to reduce the column FPN from milivolt to microvolt. Then it compares the chip test result with the simulation result to confirm its function. In addition, it introduce other applications of double sampling technique in image sensor, such as spatial double sampling and temporal double sampling. Furthermore, It analyses and compares the several capacitor array coding in PGA, and design a new three stages pipeline system structure with different coding each stage, and carefully analyses and designs each stage circuit and operational amplifier. The simulation result shows the PGA achieves 128 linear gain steps with 1/8 dB gain each step in 20 M Sampling/s clock, and it has a good linearity with low power consumption.The creative work of this article include: Design active pixel readout circuit with high fill factor (47%) which was successfully taped out. Design a column readout circuit with FPN reduction with low power consumption (16.5μW ) in small column pitch (8μm), it is also successfully taped out to confirm the function. Design a programmable gain amplifier with new three pipeline stages and mixed capacitor array coding, which achieve high linearity, low power consumption and small area.