Study Of Test Methods For Integrated Circuits

With the increasing of the density and complexity of Integrated Circuits, more and more designs adopt the methodology based on IP cores and hence DFT technique must be used to solve the IC's test problem. Scan technique and boundary scan technique are the main stream technology of current DFT technique. They can solve the internal testable problems and the connection problems between ICs respectively. In order to shorten the whole IC test time, test schedule is required greatly to implement parallel test of the cores under the constraints of power dissipation limit and test resource conflict. Boundary scan standards, including 149.1, 1149.4, 1149.5, 1149.6, can be used to solve all sorts of connection tests between ICs; As for full scan and partial scan techniques, the problems of gated-clock, clock-divider, internal-reset, tristates nets, bus contention in scan shift and controlling bidi direction, are discussed to reconstruct scan chains to improve fault coverage, furthermore, the function of DFT is added to an mutilevel filter chip and the the ATPGs for the chip are generated by the DFT tools from Synopsys Company; The most advanced low power DFT design methods are concluded, from the angle of how to reduce the toggles of the nodes of the whole design, low power DFT methods about the designs for both scan-based and non-scan based are proposed; A novel SoC test schedule model is constructed, and a practical scheduling algorithm is proposed, the experiment results show that our algorithm can be used effectively for SoC test schedule.