High-performance SOI pseudo-nMOS circuit design techniques for the deep sub-micron era

Aggressive scaling has ensured the continued use of complementary metal oxide semiconductor (CMOS) designs in VLSI systems. The characteristics of advanced devices operating at low supply voltages will be sufficiently different from those in past technologies, as to justify a fresh look at logic families in light of high leakage and other device traits. In terms of technology, due to better scalability and reduced short channel effects, silicon-on-insulator (SOI) technology has emerged as a leading candidate for mainstream VLSI design.; The dissertation evaluates pseudo-nMOS logic circuits and proposes novel, high-performance, static and dynamic circuit techniques for SOI technology. To perform realistic evaluation, an open-source, 4-way superscalar, dual-issue, fixed-point microprocessor core, along with custom testing methodology has been designed. Specific datapath units of the processor are used for evaluating the pseudo-nMOS circuit techniques. At high operating frequencies, which will be prevalent in the deep sub-micron era, pseudo-nMOS circuits offer better performance than complementary logic circuits. Simulation results are validated by measured data from hardware fabricated in a 90nm SOI technology. Compared to complementary logic, a 5x reduction in standby leakage is achieved. Pseudo-nMOS circuits allow systems to be designed closer to the maximum performance point, as the load bias can be adjusted to compensate for variability in process parameters.; Two novel dynamic circuit techniques known as controlled-load limited switch dynamic logic (CL-LSDL) and hybrid LSDL (HLSDL) are developed. The new circuit techniques offer better immunity from noise and charge sharing issues; the circuits also consume significantly lower power than LSDL circuits. Wide implementations of the CL-LSDL circuits have been shown to reduce power consumption by 50% compared to non-wide CL-LSDL implementations. HLSDL circuits offer delay improvements of 30% compared to CL-LSDL; they are found to be ideal for use with dynamic voltage scaling schemes.; The proposed static and dynamic pseudo-nMOS circuits are best suited for high-clock rate, high-switching activity circuits such as DSPs, memory decode and datapath circuits. They can be freely mixed with other logic styles. The novel circuit techniques presented in the dissertation are very relevant to present and future deep sub-micron VLSI technologies.