Research And Realization Of Satellite Image Coding And Testing Technology

The progress of image coding technique are presented at the beginning of this paper. After that, a new generation image coding algorithm– JPEG2000 is introduced and applied to a high fidelity, high ratio hardware satellite image encoder. One emphasis is on the T2 algorithm analysis and the problems coming forth in the hardware realization. A T2 encoder implementation scheme with high performance and low hardware cost is proposed which meets the real-time coding request well .In order to test the performance of the image encoder, a set of testing system is developed which is based on PCI bus and applying XILINX FPGA and PLX PCI9054 chip. The system can send out simulation image data at the speed of 64 mega bytes per second to the image encoder and collect the compressed bit stream from the encoder and store it in hard disk. Through the comparison of the data collected and the data compressed by software, the encoder's function can be verified. In the realization of this testing system, traditional interrupt mode will cause frames missing. A new implementation scheme based on FIFO is designed and the problem was successfully solved.