Design And FPGA Implementation Of Channel Coding Based On DVB-C2 Standard

With the development of the digital TV technology, microelectronic technology and signal processing technology, as well as the continuous improvement of cable TV customers' business needs, DVB project team made a second generation digital transmission system for cable systems (DVB-C2) in April 2009. Compared with DVB-C, this standard not only supports multiple input streams, variable coding and modulation, adaptive coding and modulation, can also have better performance, greater transmission capacity and flexibility. Its so powerful performance is inseparable with its advanced channel coding techniques.DVB-C2 standard has a powerful FEC system based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, and the output of the LDPC encoder shall be bit interleaved, which consists of parity interleaving followed by columntwist interleaving. LDPC code is an error correcting code with a high performance allowing Quasi Error Free operation close to the Shannon limit. It is a good choice for high-speed communications system and its encoding and decoding algorithm is simple. Cascading with BCH code has superior performance, and can be widely used in mobile communications, satellite communications, wired communications and other fields.The purpose of this subject is to complete the design and implementation of the channel encoder in line with DVB-C2 standard, using ISE and Modelsim as a design and simulation tool, with Xilinx's Virtex-5 series FPGA as a platform. By researching the practical application projects and DVB-C2 standard, this paper completes the overall structure of channel coding division, Verilog HDL code, as well as simulation.In this article the architecture of the DVB-C2 sending system and each module is introduced firstly. Then based on learning the basic theory of error correction coding and interleaving techniques, the channel coding technique of DVB-C2 is analyzed. After that, the design and implementation of an universal channel encoder is proposed. At last the simulation results of each module is given.The data rate adjustment of BCH encoder is achieved by inserting an empty packet. Using a dynamic reconfigurable PLL and an asynchronous FIFO, the data rate adjustment of LDPC encoder is also realized. The dynamic reconfigurable feature of PLL makes dynamic reconfiguration of channel coding parameters as possible. Based on this, the universal channel encoder is realized. By analyzing LDPC codes parameters'characteristics in DVB-C2 Standard, an implementation method of LDPC encoder for DVB-C2 is proposed. The LDPC encoder in this design is achieved using only one FIFO,13 RAM and ROM, and appropriate logic circuit. Compared with adopting ping-pong operation, this method saves nearly half resources. And according to different encoding parameters, the dynamic power consumption can be effectively reduced by properly shielding some RAM. To ensure data continuity, LDPC encoder and bit-interleaver uses pipeline and ping-pong operation.Finally the universal channel encoder of DVB-C2 is designed and implemented based on Xilinx's xc5vsx50t chip, supporting normal FECFrame and short FECFrame, eleven kinds of LDPC code rate and five kinds of QAM modes. After synthesized, the clock is up to 127.374 MHz, and can meet the needs of DVB-C2 standard.