Design Techniques Of P-Type CMOS Circuits For Leakage Reduction In ICs

With the fast development of IC technology, leakage power of the chips has become an important index in the VLSI designs. In the previous CMOS technology generations, dynamic dissipation is the main source of power consumptions in integrated circuits. Traditional power-efficient designs focus mainly on how to reduce the dynamic dissipations. Adiabatic computing is a new lower-power circuit design technique, and has attained a lot of dynamic power savings.In sub-micro CMOS circiurs, it is predicted that energy dissipation from static leakage current could be comparable to dynamic switching energy, and leakage power will become a crucial factor in VLSI circiurs. However, researches on the design techniques of the traditional CMOS circuits and adiabatic circuits for leakage reduction are less. With the further development of technology, gate oxide thickness has been scaled to maintain adequate control of the channel for the gate. Gate leakage power, which has almost caught up and even surpassed the sub-threshold leakage current in 65nm process, has become another major source of leakage power.The gate leakage through SiO2 for the PMOS transistors is an order of magnitude lower than NMOS. Therefore, this thesis chooses combinational and sequential circuits as research object to investigate the leakage reduction techniques by using P-type CMOS circuits.Traditional CMOS circuit adopts pull-up PMOS and pull-down NMOS transistors. This paper breaks through the structure of traditional CMOS circuits and studies the relation between logic function and construct topology of MOS transistor for adiabatic circuits. Several new circuit structures are proposes in this paper, which are dominated by PMOS transistors. Typical adiabatic circuits are chosen for designing P-type CMOS circuits, and the HSPICE simulation results show that these proposed new circuits have low leakage power consumptions.