Advanced placement techniques for future VLSI circuits

Advanced technologies are expected to reduce interconnect delays and increase transistor packing densities to allow for the continuation of Moore's Law. These advancements are enabled by the shrinking of VLSI feature sizes from one generation to the next, and through new fabrication technologies such as three-dimensional integrated circuits, with multiple active layers in a monolithic structure. As a result of these process enhancements, additional design constraints must be considered in electronic design automation (EDA) tools. Specifically, 3D circuits can face severe thermal problems if not carefully designed, since they have significantly larger power densities than their 2D counterparts and high thermal resistances between active layers. Moreover, interlayer wires that connect devices in different active 3D layers are restricted due to fabrication limitations. Another issue that arises with future VLSI circuits is the exponentially increasing number of repeaters needed to counteract the poor scaling of interconnect delays: without methods to manage and reduce repeater counts, a breakdown in the design process could result from the perturbations caused by repeater insertion.; Several aspects of performance-driven physical design at and around the placement stage are examined in this thesis to address these issues that arise in the design of next-generation circuits. First, placement techniques for 3D ICs are devised to explore the tradeoff between interlayer via counts and wirelength. Placement and legalization methods are developed using analytical and partitioning-based techniques to allow wirelengths to be minimized for any desired interlayer via density. Thermal placement is then used to reduce both power and temperature by using net weighting and additional thermal-directing nets in a partitioning-based approach. The thermal objective is retained during detailed placement in order to continue thermal optimization into legalization. Next, an algorithm was developed to reduce thermal problems in 3D ICs by incorporating dummy vies used for heat removal, called thermal vial, into placed designs. The arrangement of thermal vies is iteratively adjusted using temperature simulations until the thermal objective is achieved, with minimal thermal via usage. Finally, a method is developed to reduce repeater counts by dynamically modifying net weights in a context-sensitive manner during global placement and coarse legalization.