Techniques for efficient on-chip power delivery and accurate leakage modeling in nanoscale CMOS

Power consumption and process variations are two major issues for the VLSI circuits with sub-100nm technologies. The soaring of power consumption makes power integrity especially challenging for designers while process variation brings ambiguity to the timing analysis and power estimation. To alleviate the above challenges in VLSI design, this thesis focuses on the study and development of several novel circuits and modeling techniques to achieve high efficient power delivery and accurate leakage estimation under process variation. The connection between the two issues is also explored in this thesis.; The conventional decoupling capacitors (decaps) for supply noise suppression suffer from large area and leakage consumption in deeply scaled CMOS technologies. To overcome the drawbacks of conventional decaps, this thesis proposes two novel circuit techniques including active decap circuit and switched decap circuit which can significantly boost the performance of decaps leading to saving of both area and leakage. Theoretical models for the proposed circuits are developed and experimental results on fabricated chips are shown to verify the functionality and performance of the proposed circuits. Furthermore, a two-story power supply network is proposed to improve power integrity in low power ICs. By balancing the current flow on different supply levels, the power supply noise is effectively reduced compared with the conventional single-story network.; The width-dependent device leakage under atomistic random dopant fluctuation has not been accurately modeled by conventional square-root approach. This thesis proposes a new statistical leakage model which leads to a significant improvement of the leakage estimation accuracy compared with the conventional approach. Circuit design applications of the proposed model on both CMOS device and a cutting-edge FinFET device are explored to prove the significance of our work.; On-chip power integrity and leakage reduction have been considered separately in the previous publications. However, our research indicates that there is a strong link between the two issues. For example, the on-chip leakage flow from active devices behaves like resistors connected between supply rails and reduces the supply impedance and the supply noise. Models considering the so-called current induced damping effect are developed in this thesis to quantify the impacts of both active and leakage current on the impedance of power supply network. Results show that ignorance of this effect will lead to pessimism in the evaluation of circuit's performance. Furthermore, the strong connection between power integrity and leakage reduction is also found in the design of sleep transistors. This thesis proposes a new sizing technique for sleep transistors considering the resonant supply noise which was ignored in the conventional sizing method. Our result shows that compared with conventional sizing, the proposed technique can achieve a further reduction of the worst-case supply noise. An adaptive sleep transistor sizing circuit is also developed to deal with the sporadic occurrence of resonant noise so that the overall performance of logic circuits can be maximized.