Research And Design On The Architecture Of Low Power Microprocessor

With the distinct development of manufacturing technology of integrated circuit, the density and speed of chips have grown rapidly. The portable systems have more and more customers. Now, the low power consumption has become the 4th factor which 1C designers must take into account with speed, area and testability. As the most advanced 1C product, the processor is the core of an electronic system. So the research of low power architecture of microprocessor have been an important research direction of processor design in the future.Analyzing the energy model of digital CMOS circuit, we describe the low power design methods and their efficiency in the different level and the low power design methodology with the synthesis technique. Finally we did many research on the low power architecture of the NCS2000 microprocessor which is a 16-bit CISC processor designed by author in Aviation Microelectronic Center with our own patent. Many design methods are provided firstly. The modules studied in the paper are decoder, micro-program controller and calculator. We also study the low power design of finite state machine, which is the general form of control logic. With these studies, we did many experiments to test the theories and methods. It is proven that the processor can reduce its power efficiently with these design techniques and the way in which we do the research is hopeful. The main contributions of this dissertation are given below.The author finished the study and design of the 16-bit CISC processor NCS2000 with our own patent. This processor is designed with the High Level Design Methodology and is compatible with the inte!80286 in instruction set and timing.The dissertation analyzes the different low power techniques in many levels and compares their efficiency. In accordance with clock gating technique, the paper offer the definitions of balanced clock unit and embedded clock gating unit firstly. They are helpful to solve the problems of synthesis, clock skew and testability of circuits using the clock gating.In order to reduce the power of the decoder in NCS2000 whose structure is affected by the changeable instruction length, the dissertation proposed the definition of precise access control, which is a stretch of operand isolation. It is very fit for the part access of an module such as the access of register file.The dissertation expand the definition of ROM partition and bring about the optimized coding of micro-program, especially the latter is never mentioned in anyscientific magazine. It is very useful to implement a CISC processor with ROM, such as 80x86 and 80x87.The dissertation study the adder and shifter which are the most two components in the data path and propose the change control with sign switch in the dynamic operand change.The dissertation study the low power model of FSM and describe the decomposition of FSM specifically. We also make study of the low power FSM software, which is helpful to develop the optimized tools in the future.