The Research Of Complex Digital Circuit Boards' Testability

With the rapid development of integrated circuit, many traditional test techniques are meeting more and more challenges. In terms of test technique, whose function and status are not as the end link of integrated circuit produces, but as the front end link plays the critical role in the whole system design, thus it requires engineers to consider the later test circumstance, which is named design for test (DFT).This paper focuses on the current situation and development trend of integrated circuit testing, and studies the design for testability through actual production. Firstly, SOPE algorithm was used to quantify the controallability and observability of the circuit, summarising several design methods specifically for testability. Secondly, design and simulation of FPGA-based random logic and embedded memory BIST circuit were completed based on pseudo random testing theory and March C algorithm, and characteristic analysis was used to realize the compression and analysis of testing response signal. Next, principle of boundary scan test as another important means of systematic design for testability was described, whose focus was the hardware structure and description language. The soft core design and simulation of boundary scan structure was achieved by using VHDL. Finally, combined with actual project of company and boundary scan test principle, the use of completed method of the completeness of program and secondary development of complex digital circuit's test, such as infrastructure test, interconnection test, memory test and cluster test projects using boundary scan method were implemented by CASLAN language. The experiment maximizes the board level test coverage.