The Design Of Energy Recovery Memorise In Deep-Submicron Processes

The integration level and performance of integrated circuit have gained enhancement with the development and widely applying of deep-submicron technology in recent years. Meanwhile, the increase of system complexity and the wide application of various mobile devices make low power a chokepoint. When CMOS devices enter deep-submicron processes, the power consumption, which causes many problems, such as energy dissipation, package cost, heat with high density and so on, attracts more and more attention. Recently, for meeting the requirement of high-performance processores and portable devices embedded memories have become more popular, which take part in SoC. SRAMs become a critical part in SoC because of its high density, high speed, low power and its manufacture compatible with logic process. It has a huge numbers of transistors, and is visited frequently in the system's working time. Thus low-power SRAM design is becoming a mainstream. The power of an SRAM put forward higher request, in consideration of the area, speed and stability, and thus to reduce the consumption of memory is a difficult problem. Energy recovery memories can save a large part of the dynamic power with small additional area, and also obtain good speed and stability. However, because of its high-density and high-capacity, the further study in low-power technology for the energy recovery memory is still very important. This topic will focus on the design of the energy recovery memory in deep-submicron process.The main contents of this paper are shown as follows:The main sources of leakage current in traditional CMOS circuits are introduced in deep-submicron process. There are three main forms: sub- threshold leakage current, BTBT leakage current and gate leakage current.The structure and principle of energy recovery circuit are described and its sources of leakage current are analyzed. A power clock generator is introduced to manage the CPAL (complementary pass-transistor adiabatic logic) SRAM circuit effectively. In order to reduce energy loss of adiabatic logic blocks during idle periods, the power-gating technologies can be introduced by switching off their power clocks.New low power structures for energy recovery circuit are designed, according to its sources of leakage current. In order to verify the effectiveness of the proposed leakage estimation technology, the four-stage CPAL buffer chain is simulated. Dual threshold technology and channel length bias technology are two ideal methods. In addition, the methods for reducing the consumption of power-gating circuit and storage cell are proposed. The structure of 32×32 adiabatic register file based on two-phase CPAL with power-gating scheme is introduced, which can operate on a single-phase power clock. For comparison, a 32×32 register file based on conventional CMOS using similar structure is also implemented. Full-custom layouts are drawn, and full parasitic extraction is done. The function verifications and energy loss tests are carried out. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains obvious energy savings.Based on the above study, the paper has proposed three new low-power 32×32 energy recovery register files use two-phase CPAL, which can operate on a single-phase power clock. All circuits are verified with HSPICE in different condition, and the various simulation results are listed to show their each superiority.