Research Of Energy-efficient Nonvolatile SRAM Based On Multilevel Resistive Ram

With the scaling of the feature size of semi-conductive devices,the leakage power of the 6T static random access memory(SRAM)is dramatically increased.Especially for the frequent-off and instant-on applications like low-power energy-harvesting systems of Internet of things,conventional SRAM consumes a significant portion of the total energy due to the long standby time.Hence,it is important for the overall energy efficiency to reduce the leakage power of the on-chip memory subsystem.In recent years,Resistive RAM(RRAM)develops rapidly due to its advantages such as fast access speed,good compatibility with CMOS process and multi-level capability.Nonvolatile SRAM(nvSRAM)circuits integrate the nonvolatile memories into SRAM cells.The nvSRAM circuits achieve zero leakage power by the store operation before power-off and restore operation during power-on.One or two single-level-cell(SLC)RRAMs are employed in each previously published nvSRAM cell to realize the store and restore operations.Hence,a large number of SLC RRAMs are required in SLC-RRAM-based nvSRAM(SLC-nvSRAM)circuits.Furthermore,high writing currents are induced for flipping the SLC RRAMs between the full resistance swing which increasing the store energy.Short-circuit currents or large leakage currents are incurred in the previously published nvSRAM cells during the restore operation,leading to the high restore energy.Therefore,the previously published nvSRAM cells suffer from high store/restore energy and low energy efficiency.To lower the store and restore energy with increased energy efficiency,a novel multilevel-cell-RRAM-based nvSRAM(MLC-nvSRAM)cell utilizing the multi-level resistance characteristics of RRAM devices is proposed in this paper.The MLC-nvSRAM cell is designed to enable the logic state storage of every two SRAM cells into a single 4-level MLC-RRAM.The required number of switched RRAMs dedicated for data storage in the MLC-nvSRAM cell is reduced effectively.The average writing currents of the MLC RRAM are also decreased.The store energy of the MLC-nvSRAM cell is therefore reduced significantly.Besides,the precharging restore scheme and the optimization of multiple resistances are employed in this paper.Due to the elimination of the short-circuit currents and large leakage currents,the restore energy of the MLC-nvSRAM cell is also reduced with a high restore yield.The normal,store,and restore modes of the previously published nvSRAM,conventional 6T SRAM,and proposed MLC-nvSRAM circuits are simulated based on TSMC 65 nm process and Verilog-A RRAM model.The MLC-nvSRAM circuit provides high SRAM read and write performance which is similar to the conventional 6T SRAM circuit and high restore yield.As compared to the lowest store energy and the shortest break-even time of the previously published SLC-nvSRAM cells,the store energy and the break-even time of the MLC-nvSRAM cell are reduced by 53.97% and 52.37%,respectively.