Research Of Low Energy Consumption SRAM PUF

Nowadays there is a lot of information exchange every day and security problem can't be ignored.We often use AES or DES to encrypt information.In this process,we need many random numbers.We often use pseudo random number,but security of pseudo random number is relatively low.And for this reason,physical unclonable function,PUF,appeared.After appearance,research of PUF has been continuing.Then,this paper analyzes the most main PUF,SRAM PUF,mainly including the operation process and principle of SRAM PUF.Based on the past research on transistor mismatch,a new 6T-SRAM PUF model is proposed,and virtuoso software is used to verify the effects of transistor sizes,node capacitance and voltage rising time on the power-up state of SRAM PUF.Through this way,the optimal mismatch and the lowest power consumption of the best 6T-SRAM PUF size are found.Then,on the basis of the new model,a new 8T-SRAM PUF is proposed.Compared with 6T-SRAM PUF,two switch transistors are added to amplify the circuit mismatch.The circuit has been designed and fabricated in rohm 130 nm CMOS process.The cell array includes 64 rows * 4 columns = 256 cells.There are 7 arrays total 1792 cells.The bit error rate of two SRAM PUF circuits were measured after the taping out.The bit error rate,BER,of SRAM PUF was about 3% and 5% respectively.In the case of ignoring the 8T switch transistors,while the bit error rate was reduced to 1.9% and3.3% in the case of using the switch transistors.Then the power consumption is measured.The average current is 360 uA at 10 MHz frequency and 1V power supply and the unit power consumption is about 20fJ/bit.Finally,this paper studies the influence of transistor NBTI and NBTI influence on SRAM PUF.And uses NBTI for the post processing of the manufactured SRAM PUF.After 5 hours of NBTI treatment,the bit error rate has been successfully reduced from 5.1% to 2.7%,which achieving a 40% bit error rate improvement compared with the initial SRAM PUF.