Pure Single-phase Energy Recovery Technology

In the conventional theory of digital circuits,power dissipation of a static CMOS circuit can be expressed as P=C·V_dd²·f.Therefore,most low power VLSI design schemes locate on how to reduce C,V_dd and f.However,energy recovery circuits(ERC),which utilize dynamic power clocks to guide charging and discharging,can get rid of this limitation,minimizing power consumption.This thesis first gives an overview of the development of energy recovery technology,and then summarizes all existing typical ERCs,analyzing each one's advantages and drawbacks.Then,to eliminate the drawbacks with the existing ERCs,a researching goal,the realization of a true single-phase based ERC without any additional timing control clocks,is proposed.In chapter 4,we present a new Quasi-Static Single-phase Energy Recovery Logic family(QSSERL),a perfect solution for true single-phase operation. Unlike any other existing ERC,QSSERL uses single sinusoidal supply-clock without additional timing control voltages.This not only dramatically simplifies the clock design,but also avoids extra energy dissipation.Besides,QSSERL can operate as fast as conventional two-phase ERC counterparts.HSPICE simulation with an 8-bit Logarithmic Lookahead Adder(LLA) using static CMOS,Clocked CMOS Adiabatic Logic(CAL,an existing typical single-phase energy recovery logic),and QSSERL,under 128 randomly generated input vectors,shows that the QSSERL adder consumes only 45%of energy as in its static CMOS counterpart at 10MHz and achieves better energy efficiency than CAL when input frequency f_input＞2MHz.Operations of a 10-stage QSSERL inverter chain and a 2-bit QSSERL LLA fabricated in the charted 0.35μm standard CMOS technology has also been experimentally verified.