Design And Implementation Of Fast-settling Frequency Synthesizer

Most wireless communication standards come up along with the progress of the integrated circuit manufactory technology. Some of them set strict requirements on the settling behavior of the frequency synthesizer in the Radio Frequency (RF) front-end.Usually, the Phase-Locked Loop (PLL) is adopted as the frequency synthesizer in the RF front-end. Nowadays, the traditional charge-pump PLL is widely used in the wireless communication system. The PLL often needs large output tuning range to adapt the requirement of wideband communication, so the wide band single/multiple core Voltage-Controlled Oscillator (VCO) is often adopted. The settling behavior of such PLL is composed of digital coarse and analog fine tuning. Digital coarse tuning is defined as tracking phase while the analog fine tuning is defined as the acquisition phase. In order to improve settling behavior, it is quite necessary to reduce both the time consumed in these two phases.Two circuits are designed in the thesis to improve the settling behavior in both the tracking and acquisition phases. For the tracking phase, by modifying the traditional integer step size divider, a low power, high input frequency Multi-Modulus Frequency Divider (MMFD) with 0.5 step size is proposed, and a new Auto-Frequency Control (AFC) algorism is also designed; For the acquisition phase, a new linear range extended Phase-Frequency Detector (PFD) and Charge Pump (CP) configuration, which can reduce the impact of the cycle slip issues caused by the large reference frequency is designed. The cycle slip issues would severely deteriorate the settling behavior of the PLL using traditional PFD and CP configuration. Simulation results validate the new MMFD, the AFC algorithm and linear range extended PFD and CP configuration.