The Rearch Of The Frequency Synthesizers In The UHF RFID Readers

This paper is about the design of the UHF RFID reader frequency synthesizer part. Using UMC 0.18umCMOS process, designed to setting time of 100us, the phase noise -123dbc/hz @ 500khz, tuning range of 800Mhz ~ 950Mhz, channel width 250khz of delta-sigma fractional PLL. As the system-level target, to design low phase noise, wide tuning range and fast settling time of the frequency synthesizer, which increases the difficulty of design. To this end, this uses a delta-sigma modulator , then it will greatly reduce fractional PLL traditional spur serious problems , and optimize the PLL phase noise performance.In line with delta-sigma performance of the modulator, using a 4th order PLL, the high stability of phase-locked loop design is the difficulty of this thesis. To simplify the mathematical model of discrete domain, using it as a model to deal with continuous domains, the PFD is as a fixed gain of the module to simulate .The required loop bandwidth is less than the reference frequency of 1/10. In order to meet the wide VCO tuning range and low VCO gain, we use a digital switched capacitor array circuit which should also be automatically selected with other modules.It has effectively solved the tuning range and phase noise of the conflict.This paper also used a high-performance charge pump to reduce the current mismatch , reducing the spur performance deterioration of output.It can also reduce nonlinear effects caused by the mismatch which will deteriorate the delta-sigma modulator nosie shaping properties. The thesis completed the design from the layout level to the circuit-level , and finish the work of pre-simulation and post simulation.