A 3 micron Sigma-Delta modulator and dual modulus divider for use in Sigma-Delta modulated fractional-N frequency synthesis

This thesis describes the logic circuit design, theoretical analysis, computer simulation, standard cell layout and testing of a noise shaping CMOS fractional N frequency divider. The complete circuit has been integrated on two chips using the Northern Telecom CMOS3 3 {dollar}mu{dollar}m double metal process.; Measured results on the dual modulus divider chip indicate that the circuit is capable of dividing input signals at frequencies up to 250 MHz. When used in conjunction with the digital {dollar}Sigma{dollar}-{dollar}Delta{dollar} bitstream generator chip, the dual modulus divider provides noise shaping to suppress noise around the divided frequency, making it suitable for use in phase locked loop frequency synthesizer applications.