Research On Built-in Self-test And Built-in Self-repair For Embedded Memory

Embedded memories have been widely applied to the field of system-on-chip (SoC), because there are many advantages regarding embedded memories, e.g., high bandwidth, low consumption and low silicon area overhead, etc. Embedded memories will occupy the largest portion of a SoC (approaching 94% by 2014). Because the system with embedded memories requires high reliability, the techniques of embedded memory self-test and self-repair have significance and practical value.The main content of this paper is research on built-in self test and built-in self-repair technology for embedded memory, in order to improve the system's reliability and stability. Related to the embedded memory fault modeling, testing and diagnosis implementation and the using of high-reliability built-in redundancy analysis strategy to achieve self-repair fault unit, the main research results are as follows:This paper proposes an effective March19N(N represents the address number of memory) test algorithm for an effectively detecting fault locations and identifying variety fault types which produces in the embedded static random access memory (SRAM), consequently improving the design and manufacture process of SRAM. Firstly, faults injection into a 64×8-bit SRAM; Secondly, read and write operations of the algorithm are translated into the states of controller, and then design a built-in self-test (BIST) with diagnostic support module; Finally, using the BIST module test the injection faults, then comparing and synthesizing the test data, in order to achieve faults testing and location. When analyzing simulation results, a fault dictionary is constructed for stuck-at fault, stuck-open fault, transition fault, inversion coupling fault, idempotent coupling fault, state coupling fault and address decoder fault. The fault dictionary shows that faults have different fault signature, finally, time complexity, diagnostic ratio and BIST hardware overhead of several test algorithms is given.In order to effectively improve the higher reliability of embedded SRAM, thus ensuring the reliability of the entire aerospace electronic systems, through analysis the characteristics of the distribution of faults of embedded SRAM, the method of column block repair and row repair was used on the basis of the improved memory architecture, and built-in redundancy analysis strategy with faults in a 2-D redundancy module was proposed. This strategy efficient use of the row repair register and column repair register in order to improve the repair rate. The simulation experiments for the 64×8-bit SRAM proved the feasibility of BIRA, which ensures reliable operation of the system in the main memory and spare modules exist faults. The built-in self repair system is given on the based of high-reliability built-in redundancy analysis strategy, the system is made of three mail parts: the embedded memory array, built-in self-test and high reliability built-in redundancy analysis. Finally, the simulation shows the system diagram of the simulation results and gives the technical indicators of the various parts of the built-in self repair system, as well as the hardware overhead.The whole proposed BIST and BISR circuits were described by VHDL code. They were synthesized, placed and routed by the synthesis tool XST of Xilinx ISE. The simulations were done by Xilinx ISE ordering ModelSim SE6.0a software. The whole designed circuits were verified through Vitex2 FPGA family of Xilinx.