New memory BIST and repair methods

As chips become more memory dominant and the process of semiconductor moves to deep-sub-micron (DSM) era, detecting defects in memories and possible repairing memories become highly important. An embedded memory not only needs good test algorithms to detect defects in it, but also requires good test methods. As an embedded memory is in system paths, test methods should not affect the system operation. At the same time, the system paths around the embedded memory may change the timing of a memory when it operates in a system; that is, the embedded memory should no longer be treated as a stand-alone memory.; In this work, we attempt to test an embedded memory as a part of a system instead of isolating it from the system. The proposed ESP memory BIST accesses an embedded memory through scan cells and includes system logic around a memory into test paths so that system performance penalty is reduced and the memory is tested with the consideration of changed timing. It could be extremely important when a memory is part of the critical system paths.; Timing faults have been an important consideration in testing high-performance designs. At-speed testing has been used as a very important method to catch timing faults. The full-speed FP-MBIST proposed in this thesis achieves higher performance by performing one operation in each cycle. Because at-speed testing is required to detect timing faults, it means repair solution generation should not slow down memory testing. The proposed at-speed built-in self-repair analyzer generates repair solution without slowing down memory test. It should be noted that at-speed is not the perfect solution for timing faults as test algorithms are not specifically designed for timing faults. So in this work we also proposed tests for better timing fault testing for a specific type of memories, CAM, as CAM is more possibly in critical system paths.