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The Design Of Thetime Predictable Embedded JavaCPU

Posted on:2013-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:F YangFull Text:PDF
GTID:2218330371964531Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Currently, the mobile Internet technology and the market have shown a explosive growth.As the Apple and the Android mobile phone as the representative of the embedded portable device appears, mobile Internet trends instead of the desktop Internet.The situation fully shows the development of embedded devices have a great impact on our lives.Various embedded product updates fast,so people on the development efficiency of embedded systems have a very high requirements.Java is a web-based application language, has the advantages of high efficiency, safety, good portability and dynamic.Therefore, researchers are eager to use Java for embedded software development.In order to meet the needs of software developers,all kinds of embedded real-time Java platform emerge in an endless stream.Routine implementation has interpretive mode, advance compilation, just-in-time compilation,Java hardware accelerator, Java processors and so on.By comparing the advantages and disadvantages of each implementation,the realization of the Java processor for embedded real-time Java platform directly executes Java bytecode in hardware and performs the highest efficiency.Previous work proposed a 32-bit Java processor JPOR-32 (Java Processor Optimized For RTSJ) architecture and achieved some initial components.Based on earlier work,this paper according to execution process of Java bytecodes,optimizes the processor architecture, improves and expands the various components,combines all modules to form a complete pipeline processor.Specific work is as follows:1. The processor adds a memory module, corresponding to the pipeline increases a memory access segment.Memory implementation refers to data structures of class file, can store the class file after pretreatment.So processor can directly read the external Java bytecode files and support jump and branch instructions to read memory.2. Processor adds the control unit to connect each module.Control unit controls all instructions to flow three pipeline segments,including instruction fetch,the instruction buffer,decoding.Control unit also includes 48-bit control signal generated by different instructions to control operations of the components in execution, memory access and write back stage.3. In addition to achieve simple Java instructions in the processor, the paper also realize the complex instruction through the micro-instruction mode. Because the complex instructions including method calls and returns etc are diffcult to implement in hardware directly.This paper finally realizes 85 Java instructions on JPOR-32.The processor is verified in a FPGA chip, and the running clocks of instructions and applications are detected.The experimental results show the high performance and predictability of WCET of the processor.
Keywords/Search Tags:Java processors, Reduced Instruction-Set Computer, Memory, Field Programmable Gata Array, Worst Case Execution Time
PDF Full Text Request
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