Algorithm Research Of Face Detection Based On Adaboost And Its FPGA Implementation

Face detection is one of the important researching aspects of human-machine interaction based on the image processing, which is the fist step of face recognition and means the process that finds and locates all the faces’location, size, postures of input images. With the development of study and the application expansion, as the important part of face recognition, face detection develops up as an independent research content, it is becoming the research hotspot of domestic and foreign scholars increasingly.This paper designs a video face detection system based on FPGA. The system uses DE2development board of Altera as the hardware platform. The monitor displays the image. When there is face in the image, then the system will locate it and display the face centre ordinate and detection time.Staring from software implementation, basing on the classical principles of the adaboost algorithm, the training process and the detection process were achieved respectively and independently. Using Haar-like features represent the face character, in order to improve the detection speed uses integral figure to calculate characteristic value. In view of the training process consumed such a long time, the number of features was optimized. Through the Adaboost learning algorithm trained800face images and800non-face images in the database at MIT obtained30weak classifiers, which make up a strong classifier. Using500face images and500non-face images in the MIT databse test the effect of the classification respectively.The test result shows that the detection rate of the face images is96.4%, detection time is0.038seconds/picture,and the the detection rate of the non-face images is76.6%, detection time is0.037seconds/picture. Then, transplanted it to the embedded system based on Nios Ⅱ of DE2development board. On the hardware side, SOPC Builder is used to build the hardware system through the Quartus Ⅱ software. In order to solve the problem of timing between SDRAM controller and VGA controller uses SRAM as the cache, writes a det2_time2module to test detection time using Verilog HDL language. On the software side, uses C language programming and debugs the process of the feature extraction and detection in the Nios Ⅱ IDE. For the image of200×200pixels, the shortest test time is0.06s. This article adopts the autonomous development of training and testing procedures, the experimental resultes show that the algorithm has strong portability.The system can accurately detect human face.