Field Programmable Analog Array Architecture Research And Reconfigurable Analog Processor Research And Design

The main focus of this thesis is to develop novel Field Programmable Analog Array (FPAA) architectures and FPAA-based high performance Reconfigurable Analog Processors (RAPs). An FPAA assessment model is established from the study of state-of-art FPAA architectures; and the detailed solutions are presented to improve the Figure of Merit (FOM) of FPAA. Based on the proposed FPAA architectures, the silicon implementations and testing results of three RAP chips for field-programmable mixed-signal processing are also presented.As the feature size of transistor channel keeps shrinking, the design and verification duration of modern VLSI chips increase greatly, leading to high chip cost and long time-to-market. Motivated by the advantages of reduced cost and short time-to-market, field-programmable devices are widely used as the platform for verification, prototyping, as well as the final products implementation. Significant research has been carried out and progress has been made on the field-programmable devices, especially on digital devices such as FPGA. On the other hand, emerging field-programmable devices of FPAA and RAP can be used in field-programmable analog signal processing and mixed-signal processing respectively. However, the research on analog field-programmable devices is still lagging behind digital ones due to the critical requirements of analog signal processing. The current research on field-programmable analog devices is mainly focusing on the basic construction elements such as Configurable Analog Blocks (CABs) and the interconnections. This opens up the opportunity for high performance analog field-programmable devices in the near future.To date, various FPAA architectures have been proposed by both academia and industry. These architectures can be classified by two categories:afflicted CAB architecture and independent CAB architecture. Based on the analysis of these two FPAA categories, an FPAA assessment model is proposed. This assessment model can be used for the evaluation of different FPAA architectures. In order to improve the FOM of FPAA, a novel coarse-grained function-complementary heterogeneous CAB architecture is proposed.The design and implementation of three different FPAA architectures are presented. The first FPAA is constructed based on the traditional fine-grained homogeneous CAB architecture. The chip testing and assessing show that the FOM of first architecture is 1135. The second FPAA is based on the proposed novel coarse-grained function-complementary heterogeneous CAB architecture. The assessment of the second architecture results in the FOM of 2788. The comparison between these two FPAAs demonstrates the feasibility and effectiveness of proposed architecture. Further improvements, including architecture optimization and function integration, have been realized on the third FPAA. This fully explores the potential of coarse-grained function-complementary heterogeneous CAB architecture, and will achieve the FOM of 3551 or even higher.Based on the above FPAA cores, three RAP chips are fabricated in 0.18μm/0.13μm CMOS technology, targeting at field-programmable mixed-signal processing applications. The proposed RAPs are highly flexible in configuration, and can be used in a wide range of complex applications such as auto-adaptive filters, PID controllers, auto gain controllers, rail-to-rail high precision multiplier/divider and so on. The relative precision of the proposed RAP is higher than 99.5%, and the maximum power consumption is one order lower compared with commercial FPAA products in the same scale.