The Design Of 8-bit Turbo-51's CPU Soft-core

An 8-bit CISC Turbo- 51 's CPU soft-core was designed in this thesis. The soft-core used a Harvard architecture, in which programs and data were accessed from separate memories using separate buses, a two-stage pipeline over laps which fetched and executed the instructions, the separate module which operated the PC. It is standard 8051 instructions-set compatible. It improves the performance by reducing the machine cycle duration from the standard 8051 period of twelve clocks to four clock cycles for the majority of instructions. Typically, the instruction executing time of Turibo-51 is 1.5 to 3 times faster than that of traditional 8051, depending on the type of instruction and for the same cycles speed.The soft-core is designed by using top-down methodology. The thesis discusses the whole design and verification of Turibo-51's CPU, including system partition, redesign of the instruction's timing, design of data paths and controlling logics, synthesizable RTL code, simulation, synthesis and FPGA verification.The results of FPGA verification show that the soft-core has good performance, and is thoroughly compatible with 8051 instruction-sets, which can be reused as an embedded CPU core in many kinds of applications and be integrated in a complicated system.