Research On Low Power Test Technology Based On 3D

With the ever increasing of integration and complexity of the integrated circuits,especially CMOS(Complementary Metal Oxide Semiconductor) device dimensions enter the nanometer era, test power has become much higher than the power produced in the circuit's functional mode, so test power is going to have a very important impact on VLSI design, and it has already been a hot topic in the research and industry areas. And with the ever increasing complexity for state-of-the-art SoC(system-on-chip) designs, however, interconnects have become the bottleneck for the performance and power dissipation of giga-scale integrated circuits(ICs). Three-dimensional(3D) technology that provide abundant interconnect resources has been proposed as a promising solution to resolve this problem [1].Because of three-dimensional structure relative to the changes in the structure of 2d structure system, 2d structure of mature testing methods can't be directly applied in three-dimensional structure. Meanwhile, three-dimensional structure as its own problems to be solved urgently, such as test power distribution during testing, some local parts power density high cause"hot spots"generation, and radiating performance has always been a stumbling block in three-dimensional structure, etc. Therefore, the research for three-dimensional structure SoC of low power test method , has the extremely vital significance.In this dissertation, based on three-dimensional structure multi-core low-power test pattern generation architecture is researched, meanwhile, low-power multi-core test access mechanism TAM (Test Access Mechanism) and test temperature cooperation are investigated. We examine how to transform the multi-core chip test scheduling problem model into more than one constraint, especially power and temperature constrained resource optimization problem and we solve the problem of test power, test time and core temperature comprehensively through scheduling algorithms of three-dimensional structure. A power optimized test scheduling method is proposed, which considers both test temperature and test power factor. This method reduces the total test power substantially under safe core temperature. Experimental results for a kind of academic SoC show the effectiveness of the new methods.