| Enabled by scaling of process technologies and propelled by the convergence of multimedia communications and computation, modern very large scale integrated (VLSI) systems contain enormous amounts of circuitry with ever more diversified functionalities. Higher power and packing densities have led to more prominent on-chip thermal coupling effects among devices and interconnects, and the coexistence of digital, analog and radio-frequency (RF) modules on the same substrate further exacerbates the problem. It is not uncommon for high-performance circuits to operate at temperatures much higher than 100°C, with large across-chip temperature differentials and steep thermal gradient. The thermal dynamics of densely packed circuits can have ill effects on timing, reliability, and even the functional correctness of the designs. Temperature tracking and optimization is thus becoming of paramount importance in modern electronic design automation (EDA) tools.; In this work we tackle the thermal issues from both design and analysis perspectives. We present several efficient temperature calculation methods for electrothermal simulation at the device and chip levels for both steady-state and transient analysis. These methods are applied to reliability simulation for input/output protection circuits, cell-level placements for improving substrate thermal distribution, and temperature-sensitive timing analysis for thermally excited timing skews.; The algorithms and methods developed in this work provide a firm foundation upon which to construct a more effective framework for temperature-sensitive VLSI design and analysis. This work attempts to provide a comprehensive temperature- and reliability-conscious design solution for dealing with emerging thermal and reliability issues. |
