Designing Of Bus Controller For LX-1164 CPU

The task is to develop a high-speed Bus Controller of Lx-1164 Processor which supportMulti-Processor Bus Protocol and include DDR SDRAM Controller that can be run withSamsung DDR SDRAM Chip.To accomplish the assignment we use WishBone Bus Protocol, and for Multi-Processorwe modify the Bus Cycle to support MOESI Snoopy Protocol. We also design the DDRSDRAM Controller which is embedded in Bus Controller. This Bus Controller have ability toaccess Samsung DDR SDRAM Chip, Precharge and Refresh.On the hardware implementation, we use ASIC design method and use advanced EDAtools to design logic and simulator. The scheme use 0.18us technique cell of SMICCorporation, it make the goal on the frequency of 400MHz.