The Theoretical Analysis And Simulation Of A HVT Structure MOSFET

As transistor sizes continue to shrink and Moore's Law progress becomes more difficult,it is expected that existing Fin FET structure will be replaced by the GAAFET structure at the 3 nm process node.IRDS predicts that the channel length of the GAAFET will shrink to the limit at 9.6 nm for the 1.5 nm process node.After that,devices will rely on three-dimensional stacking to increase integration,and Moore's Law will come to an end.We proposed a new type of Hetro-junction Vertical Tranch Field-effect Transistor(HVTFET).Its working principle is different with the fully-depleted principle that used by the Fin FET and the GAAFET.The heavily doped channel region and lightly doped drain region of the HVTFET can effectively suppress the short channel effect,so that HVTFET can break through the minimum channel length of the GAAFET and continue to shrink.The specific work done in this thesis is as follows:This thesis describes the basic structure and working principle of HVTFETs.As a vertical structure device,the HVTFET uses an epitaxial growth with self-doping process to make a heavily doped channel region and a lightly doped drain region,which is completely different from the lightly doped or even undoped channel region required by the fully-depleted principle.The advantage of the HVTFET is that the channel length is only determined by the thickness of the epitaxial layer and does not depend on the lithography accuracy.The epitaxial growth with self-doping process can effectively avoid the random fluctuation of impurity concentration.The heavily doped channel region and lightly doped drain region of the HVTFET can effectively suppress the short channel effect and high field effect.The gate of the HVTFET does not need to surround the channel region all-around.Hence the W/L of the device can be flexibly adjusted to save the chip area.The three-dimensional modeling of the HVTFET is carried out with TCAD software.And multiple sets of characteristic parameters of the HVTFET are extracted through simulation to analyze the working performance of the HVTFET.In this thesis,six groups of structural parameters are set to test the influence of themselves on the device when they are independently changed.The optimization method of the HVTFET when the size is reduced is summarized according to the simulation results.This thesis models the Fin FET and the GAAFET devices using a similar approach to the HVTFET.Simulation and optimization of the Fin FET,GAAFET and HVTFET with channel lengths of 20 nm,16 nm,12 nm,8 nm,and 4 nm.The simulation results show that the Fin FET and the GAAFET do not work properly when the channel length is reduced to8 nm and 4 nm,respectively.The HVTFET still has good performance when the channel length is 4 nm.Its DIBL value and SS are 31.7 m V/V and 93.8 m V/dec,respectively,which meet the requirements for normal operation of the device.