Σ-Δ Fractional-n Frequency Synthesizer System Design For China Mobile Multimedia Broadcasting Tuner

TakeΣ-Δfractional-N synthesizer which applies to CMMB tuner as an example,this thesis carried out a thorough study of theΣ-Δfractional-N frequency synthesizer in four aspects as the system modeling, performance optimization, functional verification and circuit design.The thesis firstly reviewed the basic principle of fractional-N frequency synthesizer. The basic principles, design considerations and common structures of sigma-delta modulation were carefully studied. A linear model of the CP-PLL was introduced. Time and frequency domain models of the frequency synthesizer which includes variable fractional division ratio were established and applied to get PLL system transfer function.Then specification of CMMB frequency synthesizer was given. A systematic analysis of the parameter optimization solution for 4th order PLL was done in this thesis. The chip area was also optimized by the proposed PLL design methodology with good phase noise prefromance and dynamic response.A dynamic behavioral model for fractional frequency synthesizer was also developed in this thesis. With the developed model, performance of different high order digital Sigma-Delta Modulators were compared and one was chosen for final design. Moreover, the thesis did functional verification for the whole loop. Accurate time domain response and spectrum were also achieved by the developed model.Using joint simulation of Matlab and Modelsim, digital circuits including SDM, counters and control circuits for theΣ-Δfractional-N synthesizer were designed and verified in the whole loop. All circuits were implemented by SMIC 0.18μm 1P6M CMOS. Simulation results showed that the developed PLL system can meet the specification of CMMB tuner, and total capacitance of the on chip 3rd order passive loop filter was only about 230pF which also satisfied with the area optimized design target.